Computer Architecture Lab

Computer Architecture Lab

Shiraz University - CSE Dept
mehdi.haji@gmail.com

The goal of this course is to design, simulate and synthesize basic hardware components of a computer system. In this semester, we tried to put away LogicWorks and use some VHDL tools instead, in order to show how VHDL can be used effectively in design. Unfortunately most of the students didn't realized the power of VHDL, and they now use their own preferred tools such as LogicWorks and CircuitMaker. So for next semesters, the goal is again: TOWARD VHDL.

Lab1: 3-bit fast multiplier related files: LAB1.CCT Lab2: Carry Look Ahead Adder related files: 74181(FC).pdf 74182Carry.pdf LAB2.CCT Lab3: Bus related files: LAB3.CCT Lab4: Control Signals Generator related files: reg.vhd shift_reg.vhd seq_design.vhd counter.vhd counters.vhd LAB4.CCT Lab5: EPROMs - Software Control Signals Generation related files: rom01.vhd waveform.vhd LAB5.CCT PROM.HEX HADY.HEX Lab6: Introduction to RAMs related files: LAB6.CCT Lab7: Introduction to Registers related files: LAB7.CCT Lab8: A simple processing unit related files: LAB8.CCT Final Exam	Download student version of MaxPlus from http://www.altera.com/ ~ 50MB
	Download VHDL Studio ~ 5MB Powerful and Easy to use!

Computer Architecture Lab

Download VHDL Studio ~ 5MB Powerful and Easy to use!

Download VHDL Studio ~ 5MB
Powerful and Easy to use!